Zybo is an embedded development platform based on the smallest model Z7010 SoC in the Xilinx Zynq-7000 series. The zybo integrates a rich multimedia peripheral interface. The powerful Z7010 chip supports the completed system design and five Pmods. The interface provides a wealth of expansion space, presumably many people have heard of the name of zedboard, in fact, it can be said that zybo is a mini-zedboard. The Zybo full stack development tutorial is divided into three parts: custom IP, porting the Linux operating system, writing driver modules and applications. Through these three parts you will be fully familiar with the development process of the Zynq AP SoC architecture, including FPGA logic circuit design, software programming, Linux operating system and software development, and how to apply these skills in the Zybo development board.
In this tutorial, we will use the Zybo Base System Design provided by Digilent's official website as the basis. Its architecture is shown in the figure. It can be seen that UART1 is connected to USB-UART, SD0 is connected to SD Card Slot, USB0 is connected to USB-OTG port, Enet0 is connected to Giga-bit Ethernet Port, GPIO is connected to Btn4/5, and Quad SPI is connected to on-board QSPI Flash. The hardware IPs in these Processing Systems (PS) are connected to peripherals on the board through a multiplexed I/O interface. In the Programmable Logic (PL) section, we have IP cores such as HDMI Tx Controller, VDMA, I2C, and GPIO. More information can be found in the files included in the download of this Zybo basic system.
Before the tutorial begins, we need to make clear the following information:
Zybo Board hardware board
Vivado 2014.1 Webpack Software Development Environment
Zybo Base System: Basic layer configuration of the board
U-boot: related to ZYBO board hardware design
Linux kernel source
Root file system
Note: Relevant information can be found on Digilent's GitHub account (ie https://github.com/DigilenTInc)
Custom IP is to let users implement their own functional module logic design in the FPGA part of Zynq SoC:
Step 1: Download the zybo base system file
Download the zybo base system archive file according to your design and extract it to the specified directory.
Step 2: Open the zybo base system file using the vivado tool
First we need to set Vivado environment variables, there are four options are setTIngs64.sh, setTIngs32.sh, setTIngs32.csh and settings64.csh, please use according to the machine system is 32-bit or 64-bit and bash version.
Step 3: Delete the existing LED module
First of all, we must ensure that all IP module status is kept up to date. If there is an update, a yellow prompt bar will be displayed at the top, click upgrade, and then an LED module has been preset in the base system. Mainly using the PS I / O interface, we have to delete this IP (as shown in the second picture).
Step 4: Set up the ip core Vendor
Before creating the myLed IP core, we need to set the name of the Vendor option in the Project Settings. Otherwise, the Vivado software will be internally anomalous. The name can be set freely according to your preferences.
Step 5: Create a myLed IP module
Click the menu bar Tools->Create and Package IP, the dialog box that pops up select Create a new AXI4 Peripheral, then enter the IP name, version, storage location and other related information in the pop-up dialog box, click Next to continue to the next step.
Step 6: Add module interface
myLed IP uses AXI4 peripheral interface, the interface type is Lite, the mode is Slave, the data width is 32bits, the number of registers is 4, and the name option is S_AXI. In fact, we only need one register, but the minimum is set to 4.
Step 7: Edit the IP function logic code
After the basic setup is complete, click Next. We need to select Edit IP and then add the user-defined logic. We need to modify two files, namely MyLed_v1_0_S_AXI and MyLed_v_0 (corresponding to the order of the above figure). After the above modification, we connect slv_reg0[3:0] with the input port led[3:0].
Step 8: Encapsulate the IP module
Through step 7 we define the IP logic, then we need to package it as a black box, select Package IP in the Project Manager drop-down menu, and follow the prompts to make sure that the options on the right side of the pop-up dialog box are all green.
Step 9: Add the custom IP myLed_v1.0 to the system
Right-click on the blank of the block design and select add IP. Search for myled to find the IP that was just encapsulated. After adding the myLed_v1.0 module, a green prompt box will appear at the top of the dialog box. We click Run connection Automation, which will connect the AXI4-Lite bus of myLed IP to the PS.
Step 10: Connect an external led port
Right click in the blank space to select Create Port, set to output, bit width led[3:0], then use the mouse to drag and drop this output port to connect with the output interface led[3:0] of myLed_0.
Step 11: Modify the constraint file to generate a bitstream file
Open the base.xdc pin constraint file under the Constraints drop-down menu, and bind led[3:0] to the FPGA hardware pins, that is, connect to the four led lights on the zybo board, and finally select in the Program and Debug drop-down menu. Generate Bitstream, at this point custom user IP and generate bitstream file completion.
In the next article, we will introduce you to the Linux operating system based on the content of this article, and further understand the development model of Zynq SoC.
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