The overall design of a video surveillance system based on FPGA is presented in this paper. The system begins with the configuration of the video processing chip via an I2C bus module implemented within the FPGA. This module allows for flexible control over the video acquisition process. Following this, the video signal is processed and stored in an SDRAM buffer using a ping-pong mechanism to ensure continuous data flow. Finally, the video is sent to a VGA display according to standard timing protocols. The entire system was developed using Verilog HDL, simulated with Modelsim, and implemented on a Virtex-II XC2VP30 FFG896 development board.
A typical video surveillance system includes components such as a light source, camera, video conversion unit, digital image transmission and control system, input/output units, and a monitor. Traditional systems rely on industrial PCs and video capture cards, which are expensive and often unstable. In contrast, FPGA-based systems offer advantages such as shorter design cycles, higher flexibility, and improved system reliability. Verilog HDL, being similar to C, provides an efficient and user-friendly approach to hardware design. This paper combines these strengths to propose an advanced FPGA-based video surveillance system.
The system is divided into five main functional modules: the video interface module, video conversion module, asynchronous FIFO module, image storage module, and VGA control module. Each plays a crucial role in ensuring the smooth operation of the system. The video interface module configures the SAA7113 video capture chip via the I2C bus, while the video conversion module decodes the video stream and converts it into RGB format. The asynchronous FIFO module ensures synchronization between the video processor and SDRAM, and the image storage module uses a ping-pong mechanism to store and display images efficiently. Lastly, the VGA control module generates the necessary synchronization signals for proper display.
The video acquisition module uses the SAA7113 chip, which supports multiple input formats and outputs ITU-R 656-compliant YUV 4:2:2 data. The I2C communication protocol is used to configure the chip, and the data is then decoded and converted into RGB format for display. The conversion from YUV 4:2:2 to YUV 4:4:4 involves interpolation and clock division to achieve the required pixel rate. Color space conversion is performed using standard formulas to generate RGB values.
The asynchronous FIFO module acts as a buffer between the video processor and SDRAM, managing data flow at different clock speeds. It uses dual-port RAM and includes control signals for read and write operations. The SDRAM control module handles initialization, refresh, and command execution to ensure reliable data storage. Finally, the VGA control module generates the necessary timing signals for output through the FMS3818 DAC.
The system's hardware connections include a camera, FPGA, SAA7113, SDRAM, and VGA display. This setup allows for real-time video processing and display. The design follows a top-down approach, breaking down the system into manageable modules that can be individually optimized. The use of Verilog HDL enables easy modification and integration with other systems, making it suitable for future enhancements like pattern recognition or intelligent video analysis.
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