Channel estimation is a key technology in OFDM. Its purpose is to give the channel parameters required by the receiver for channel equalization, signal detection, channel quality measurement, and soft decoding. Its performance is directly related to the error of the entire OFDM communication system. Rate performance [1] [2].
The channel estimation method of OFDM based on reference signal (RS) mainly includes LS algorithm and MMSE algorithm: LS algorithm is simple and suitable for general wireless environment; MMSE algorithm has high reliability, but it is too complicated [3] [4]. The channel estimation on the OFDM system combined with MIMO technology should consider the separation of the pilots received by each receive antenna from multiple transmit antennas, and the coordinated processing of the received data from multiple receive antennas [5]. At present, there are relatively few design schemes for channel estimation of MIMO-OFDM system on FPGA. In some traditional schemes [5]-[7], each channel needs to set up a channel estimator to estimate the pilot channel frequency response, interpolation It is estimated to be realized by a complex multiplier, which will consume a lot of hardware resources. This article is based on the MIMO-OFDM system in [8], and the channel estimation scheme is designed and implemented on the ML605 development board. According to the system application environment, considering resource consumption and complexity, LS estimation algorithm and linear interpolation algorithm are used for modular design, which has good scalability. Based on the traditional channel estimation scheme, the LS estimation module is simplified, and the interpolation coefficient calculation of the interpolation module is optimized to reduce the consumption of FPGA arithmetic units and storage units. After testing, after adding this solution to the video transmission system, the video signal is clear and stable.
Figure 1 shows a two-layer physical layer receive link model for real-time video transmission. After the OFDM demodulation at the receiving end, the user data signal and the reference signal are separated. The channel estimation module utilizes the conjugate multiplication of the received reference signal and the locally stored reference signal to obtain the channel parameters [9]. According to the MIMO diversity space frequency decoding formula, the user data signal and channel parameters are sorted out and output to the MIMO decoding module for Processing to reduce wireless channel interference. The system global clock frequency is 100 MHz, the system bandwidth is 10 MHz, and the number of subcarriers is 600. MIMO uses 2T & TImes; 2R antenna matrix.
3. Overall design of the channel estimation moduleIn this paper, the channel estimation module design is first modeled on Xlinx ISE using VHDL language and added to the receiving end chain
Figure 1. Architecture of receiver of video transmission system
Figure 1. Video transmission system receive link model
Carry out simulation testing in the road; then mount the physical link as a hardware peripheral on the Xlinx XPS to the system, configure the Microblaze IP core; finally download the receiving end and sending end programs to two ML605 development boards, and send The camera and video server are connected to the receiver, and the receiver decodes through the decoder, and the video image captured by the camera can be seen on the display.
The channel estimation module uses a two-layer link structure to process the received data of the two receiving antennas. The top module consists of four modules: LS estimation module, interpolation module, data processing module and output module, as shown in Figure 2.
In FIG. 2, RS00 and RS10 respectively represent reference signals sent by two transmitting antennas received by receiving antenna 0, and RS01 and RS11 respectively represent reference signals sent by two transmitting antennas received by receiving antenna 1. After receiving the reference signal (Reference signal, RS), the LS estimation module estimates the channel parameter hls of the RS location and outputs it to the interpolation module; the interpolation module uses the received pilot location channel parameters according to the pilot pattern, through Frequency and time domain interpolation calculates the channel parameter h of the user data location and stores it in RAM; the data processing module receives the user data, organizes the data into the format required by the MIMO decoding module, and outputs it to the output module; the output module uses the slave OFDM The user data address received by the demodulation module extracts the channel parameters of the four channels (two transmit antennas to two receive antennas) corresponding to the user data location from the RAM, and outputs the user data together with the channel parameters.
In order to facilitate the optimization and upgrade of the physical link in the future, each function adopts a modular design, the external interface of the module adopts the AXI-Stream interface, and the data buffer connection between the modules is through a FIFO with an AXI-Stream format interface, as shown in Figure 3 .
Under the AXI-Stream protocol, when the rising edge of the clock comes, the two handshaking signals of READY and VALID at the receiving end or the sending end are both "1" to complete a data transmission. When the READY signal output by the FIFO is "1", it indicates that the FIFO is not full; when the FIFO output VALID signal is "1", it indicates that there is valid data in the FIFO.
The video transmission system uses the LTE downlink specified frame structure and pilot pattern [10], as shown in Figure 4. The white squares in the pilot pattern represent resource particles (REs) carrying user data and control information, the black squares represent REs carrying pilot data, and the crosses represent blank REs carrying no information.
3.1. LS estimation module
The LS estimation module mainly uses the LS algorithm to estimate the channel parameters of the RS position 
. Let the received RS be 
, The locally stored RS is 
. According to the LS algorithm:
(1)
due to 
versus 
Are plural, suppose 
, 
, After bringing into formula (1), we get:
(2)
According to equation (2), the binary tree pipeline technique is used to design the LS estimator. The binary tree pipeline structure can give full play to the advantages of FPGA parallel pipelines, improve system calculation efficiency, and reduce register consumption. When designing a pipeline, you first need to select the appropriate pipeline stages to reduce processing delay. For example, for N data to participate in the processing, and need to be multiplied or added to the calculation of the result of the calculation, the pipeline stage should be set to 
. Secondly, each stage of the pipeline cannot bear too much calculation, otherwise it will reduce the overall pipeline processing speed. The design of the LS estimator in this article uses a three-stage pipeline, each stage of the pipeline undertakes an operation task, and delays one clock cycle, as shown in Figure 5.
Figure 2. Architecture of channel esTImaTIon module
Figure 2. Top-level structure of the channel estimation module
Figure 3. Architecture of AXI-Stream interface
Figure 3. AXI-Stream protocol interface structure
Figure 4. The frame structure and the double-antenna pilot pattern of the system
Figure 4. System frame structure and dual antenna pilot pattern
After the local RS is generated by Matlab, it is stored in the ROM, and the ROM address is controlled by the state machine to output the corresponding RS. In the traditional channel estimation scheme, each receiving antenna requires two LS estimators to estimate the RS location channel parameters [5] [6]. Taking the RS received by antenna 0 as an example, RS00 and RS01 require an LS estimator and a ROM that stores the local RS for parameter estimation. Since the RSs sent by antenna 0 and antenna 1 are the same, in this scheme, after combining RS00 and RS01, the state machine control is used to alternately input to an LS estimator, which reduces the use of resources such as arithmetic units and ROM by half.
3.2. Interpolation module
The interpolation module performs linear interpolation based on the pilot pattern. First, frequency domain interpolation is performed, taking the pilot pattern transmitted by antenna 0 as an example. The frequency domain interpolation formula is shown in equation (3).
among them 
Indicates the RS interval in the frequency direction, 
Frequency 
,time 
Channel response at location. The channel parameters between the RS positions on the OFDM symbol where the RS is located (symbol 0 and symbol 4, taking symbol 0 as an example) are estimated by hls obtained from the estimation module, and stored in the corresponding FIFO. There are 100 RSs in each symbol, so it loops 99 times. After the loop, the channel parameter of the subcarrier at the edge is directly assigned to the channel parameter of the nearest RS position. The process is shown in Figure 6.
Then perform linear interpolation in the time domain. The interpolation formula in the time domain is shown in equation (4):
among them 
Indicates the pilot interval in the time direction, 
Frequency 
,time 
Channel response at location. The channel parameters of symbol 0 and symbol 4 obtained by frequency domain interpolation in fifo are used to estimate the channel parameters of all subcarriers on other symbols, which are mapped to the corresponding addresses in the corresponding symbol RAM to facilitate the output module to use the received data The address reads the channel parameter at the corresponding position. Since the number of system configuration subcarriers is 600, the setting cycle is 600 times. The channel parameters of each symbol of symbol 0 and symbol 4 in time domain interpolation need to be used twice, so after the first reception and interpolation calculation, the symbol channel parameters will be stored in temporary fifo (temp) for the next Round interpolation is used. The process is shown in Figure 7.
In order to reduce the limited multiplier resource consumption in FPGA, the input data shift calculation is used to calculate the interpolation coefficient. The traditional interpolation estimate is that the denominator of the interpolation coefficient is not 
At this time, it is necessary to use a multiplier to multiply the input data and the interpolation coefficient stored in the ROM in advance [7]. In this design, when the denominator of the interpolation coefficient is not 
, Choose to increase the length of the 8-bit data decimal place in the lower bits of the data, and shift to calculate multiple of the original data 
One part is obtained by adding the binary tree pipeline and then intercepting the high 16-bit data. As shown in formula (5) (6) (7) (8), the coefficient error is controlled at about 1/213.
3.3. Data processing module and output module
The MIMO transmit diversity scheme selects the space-frequency coding of the LTE standard. When the MIMO decoding module performs maximum likelihood decoding, it is necessary to receive corresponding user data and channel parameters to construct a decision vector. According to the decision vector construction formula, each time the decision vector is constructed, the user data on two consecutive REs on the two receiving links and the channel parameters of four channels are required to participate in the calculation [11]. The data processing module serially merges the user data on two consecutive REs in the received two-layer link, and then outputs it to the output module. The output module calculates the average value of the channel parameters of the two RE addresses according to the received user data address, and outputs it to the MIMO decoding module together with the user data.
3.4. Comprehensive testing and simulation
After the modeling is completed, it needs to be synthesized on ISE. After synthesis, you can view the resource consumption of the channel estimation module in ISE, as shown in Table 1.
Figure 5. Architecture of LS esTImation module
Figure 5. Internal structure of the LS estimation module
Figure 6. The flow chart of frequency domain interpolation
Figure 6. Frequency domain interpolation flowchart
After the synthesis is successful, the channel estimation module is added to the entire MIMO-OFDM physical transceiver link, and the data source is input at the sending end, and simulation is performed using Modelsim. In order to perform calculations on the FPGA, all data has been quantized to 16-bit fixed-point decimals, where the highest bit is the sign bit, the next highest bit is an integer bit, and the remaining 14 bits are decimal places, so the data range is between −2 ~ + 2 . The channel parameter output is shown in Figure 8.
Despite the introduction of fixed-point errors and intercept errors in the data processing, the fixed-point 16-bit data (CH00_OUT_RE and CH01_OUT_RE) of the real part of the channel parameters of channel 00 and channel 11 are still close to 16,384 (that is, 1). In a wired environment, since channel 01 and channel 10 do not receive data, the fixed and 16-bit data of the real and imaginary parts of the channel parameters are close to 0 (0). The input and output of the MIMO-OFDM baseband transmission link is shown in Figure 9, where the valid signal indicates data validity. After the data is input to the sending end (tx) of the link, the receiving end (rx) outputs the data accurately and without loss. Therefore, the channel estimation module can enable the system to correctly restore the transmitter data under the wired environment.
4. Video transmission testMount the sender and receiver of the designed physical layer link as peripherals in the XPS project. Configure the Microblaze IP core in the ML605 development board to receive and encapsulate the video information sent by the video server at the sending end, and send it to the physical layer link through the logical channel; receive and parse the physical layer data information at the receiving end and send it to the video Decoder decoding. Microblaze IP core and physical layer link carry data transmission through PLB (Processor Local Bus) bus. After the configuration is complete, download the generated bitstream file to ML605
Table 1. Hardware resource consumption
Table 1. Hardware resource consumption
Figure 7. The flow chart of time domain interpolation
Figure 7. Flow chart for time-domain interpolation
Figure 8. Simulation of channel parameters output
Figure 8. Channel estimation module channel parameter output simulation
Figure 9. Simulation of input and output of MIMO-OFDM link
In the development board, set up the camera and video server. After the video stream at the receiving end is decoded by the decoder, the video captured by the camera can be seen on the display, as shown in Figure 10. Two sets of equipment are placed in two adjacent laboratories, you can see the images captured by the local camera and the received
Figure 10. Video transmission test
Figure 10. Video transmission test
The image is clear and stable, which verifies that the channel estimation module can effectively resist channel fading in a simple laboratory environment and improve the system transmission reliability.
5 ConclusionIn this paper, for the MIMO-OFDM video transmission system, the LS algorithm and linear interpolation algorithm are used to design a channel optimization scheme that optimizes the structure and consumes less FPGA logic resources, so that there is enough space on the FPGA chip for further physical layer links. design. It supports a maximum clock frequency of 282.509 MHz. After testing: after adding channel estimation, the video transmission system can perform wireless video transmission in a simple and fixed environment in the laboratory, and the image is clear and stable.
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