Abstract: Introduced the digital down-converter CCl012B, and used this chip to construct a programmable digital radio structure OFDM  transmission system receiver.
Modern broadband radio receivers increasingly emphasize the digitalization and programmability of hardware platforms. This is particularly prominent in the process of moving towards software radio. The concept of programmable digital radio (PDR) is put forward under this background. It refers to the use of band-pass sampling, multi-rate signal processing and digital down-conversion technology as the theoretical basis, using programmable devices CPLD, FPGA And DSP's flexible reconfigurable and powerful digital processing capabilities to build a digital, programmable radio hardware platform. PDR structured hardware platforms usually have rich bandwidth and good real-time performance. This structure is widely adopted in receivers for broadband systems such as WCDMA and WLAN.
Digital down conversion technology is a core technology in PDR. Its function is to carry out spectrum shift on the digital signal after A / D, and combine with signal processing such as spectrum inversion, extraction, filtering, etc. to achieve the purpose of down conversion and separation of spectrum components. The signal after digital down conversion is usually a baseband signal with a reduced rate.
The digital downconverter is composed of three parts: digital mixer, digitally controlled oscillator and low-pass filter. In terms of working principle, digital down conversion is the same as analog down conversion, that is, a signal is input and a local oscillation signal for multiplication. However, since the digital down-converter uses a digital local oscillator, its frequency conversion accuracy and resolution can be very high, such as the frequency resolution of GCl012B is 0.1 Hz. DDC's frequency stepping, frequency interval, etc. have ideal performance. In addition, its control and modification are relatively easy. These are difficult to compare with analog down converters.
This article uses the digital downconverter GCl012B to construct a PDR structure OFDM transmission system receiver.
1 System design
In the receiver to be designed, the received signal is an OFDM signal with an intermediate frequency of 70 MHz and a bandwidth of 10 MHz. Different from the traditional receiver structure that simulates the down conversion of 70MHz IF signal and then samples, in the PDR structure receiver, the IF is directly sampled at a sampling frequency of 80MHz, and then the sampled signal is digitally down converted and 4 times of decimation filtering, the baseband signal with a rate of 20M Baud is sent to DSP and FPGA for demodulation. The purpose of the rate reduction is to reduce the computing load of DSP and FPGA. The circuit structure is shown in Figure 1.
2 GCl012B and its configuration
Since Graychip (now acquired by TI) launched the world's first digital downconversion ASIC, many companies have developed digital downconversion chips. The more famous ones are Harris (renamed Intersil in 1999), ADI And Stanford Telecom.
The digital down converter used in the circuit is GCl012B from Graychip. GCl012B is a 3.3V power supply CMOS device, the maximum sampling rate of the input signal is 100MHz, and the bandwidth is 50MHz. GCl012B is not compatible with the 5V level. Do not connect the 5V electrical signal directly to any of its pins, otherwise it will damage the device. Internal modules include numerically controlled oscillators, digital mixers, variable rate decimation low-pass filters, adjustable gain amplifiers, data format selection modules, etc. Through the microprocessor interface to configure internal registers can change the chip's working state. Its structure is shown in Figure 2.
The chip is packaged in a 120-pin QFP, and the power consumption is about 900mW in the case of 3.3V power supply and 70MHz signal input. The dynamic range is above 75dB, the frequency resolution is 0.1Hz, and the gain adjustment step is 0.03dB. The output mode of the chip has two options: real and complex. When set to real number mode, only output data at I port; when set to complex number mode, output two orthogonal data of I and Q. The input data width is 12 bits, and the output data width is 16 bits.
The working state of GCl012B is determined by the control word in the internal register. When the system is powered on, you can use a single-chip microcomputer to configure it through the microprocessor interface with GCl012B. The tuning frequency is determined by the 28-bit FREQ according to (1), where fs is the sampling frequency of the input signal.
In this system, the sampling frequency is 80MHz and the tuning frequency value is 10MHz, so FREQ: (2000000) HEX. GCl012B synchronizes the data and status word according to the SS # signal, converts to baseband, performs 4 times extraction and flips the spectrum, and outputs I and Q data in a complex form.
The process of spectrum conversion is shown in Figure 3, where F represents the analog frequency, which is the actual frequency of the signal, and f represents the digital frequency, which is the frequency normalized by the sampling frequency. Sampling an analog signal with a center frequency of 70MHz and a bandwidth of 10MHz (as shown in Figure 3 (a)) at a frequency of 80MHz to obtain a signal with amplitude-frequency characteristics as shown in Figure 3 (b). For the period extension, only the main period of the signal spectrum is drawn in the figure. Figure 3 (c) plots the signal after digital down conversion, the signal spectrum is shifted to the left by 10MHz. After low-pass filtering, only the signal near zero frequency is retained, as shown in Figure 3 (d). In order to ensure that the signal has no aliasing after 4 times of extraction, the digital bandwidth of the low-pass filter must be set to 1/16. The signal after 4 times of extraction is shown in Figure 3 (e). You can see that the digital spectrum of the signal has been widened 4 times. Note that the positive frequency domain spectrum of the signal is inverted when the signal is sampled, so the extracted spectrum is inverted again to recover the OFDM baseband spectrum, as shown in Figure 3 (f).
The core processing part of the receiver, DSP and FPGA, after receiving the baseband signal with the rate reduced to 20M Baud, performs synchronization, channel estimation, equalization and demodulation on the signal, thus completing the receiver function.
Digital down-conversion technology is a key technology for building programmable digital radio structure receivers. It makes the band-pass sampling of the wideband signal at the intermediate frequency practical, and the frequency spectrum of the signal concerned by the system can be accurately separated from the sampled signal and down-converted to baseband.
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