Design of CAN Node of Vehicle Controller of S12X Series Dual-Core Single Chip Microcomputer

Abstract: MCG9S12XE series dual-core single-chip microcomputers with XGATE core have the advantages of fast data processing speed, short response time, low power consumption, etc., and have good application prospects in the field of automotive electronics. This article introduces the advantages of Freescale's MC9S12X series dual-core single-chip microcomputer in the hybrid vehicle controller, and gives the design and execution flow of its hardware interface for CAN bus communication. Finally, the typical configuration method of using the coprocessor XGATE to manage CAN bus communication is given.

Keywords: vehicle controller; CAN; MC9S12XE; XGATE; interrupt


The high-precision, high-speed, and high-reliability hybrid vehicle controller is the basis for vehicle control. In order to avoid electromagnetic interference in the vehicle-mounted environment and satisfy the fast response of the closed-loop control system, the communication between the vehicle controller and other controllers adopts CAN bus. The maximum bit rate of the CAN bus can reach 1 Mb / s, which can meet the high-speed communication between the vehicle controller and the outside world.

Freeseal's MC9S12XE (S12X for short) series of single-chip microcomputers are specifically designed for automotive networking and general body applications. They have the performance of a 32-bit single-chip microcomputer and all the advantages and functions of a 16-bit MCU. The internal enhanced XGATE module allows high-speed data to independently transmit and process data between the peripherals of the microcontroller and the internal RAM and I / O ports. XGATE has a 16-bit reduced instruction set core built-in, which can transfer the data to be transmitted. Preprocess and execute complex communication protocols, easy to program in C language. Reasonable use of XGATE can increase the communication speed of the vehicle controller and the external CAN bus without increasing the interrupt load of the main CPU (S12X CPU), thereby improving the data processing capability of the single chip microcomputer.

1 CAN bus hardware interface design

The schematic diagram of CAN bus node interface of S12X dual-core microcontroller is shown in Figure 1. In order to enhance the anti-interference ability of the CAN bus node, the CAN bus transceiver pin of the S12X single-chip microcomputer is not directly connected to the TxD and RxD of the PCA82C250, but is connected to the PCA82C250 through the high-speed optocoupler 6N137, so that the bus is well realized. Electrical isolation between CAN bus nodes.

Two capacitors C1 and C2 are connected in parallel between the CANH and CANL pins and ground, which can filter out high-frequency interference on the bus and have a certain ability to prevent electromagnetic radiation. In addition, TVS tubes D1 and D2 are respectively connected between the two CAN bus input terminals and the ground, which can play a protective role when transient interference occurs between the two input terminals and the ground.

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