Seeing a cow's understanding of the FPGA, it seems that the FPGA is too powerful!
In most cases, the cost of the chip is about 100 times that of the ASIC. The biggest waste is in the LUT. To make a LUT-4, you need a 16-bit memory cell, plus a 4-16 decoder, and others. The connection resources, made a LUT-4, need at least 16 & TImes; 6 + 8 transistors. Then do a 4 input logic, if you design well, use up to 8 transistors with transistors. Assuming that the LUT is used, it is equivalent to using 13 times the transistor to do the same thing. MUXF and MUXCY account for a much smaller number of transistors, and these components will be much faster. The LUT is essentially a 16-bit memory, the FD is a 1-bit memory, and the FPGA is essentially a large amount of memory. When the LUT and FD of the FPGA are used as much as possible in the memory, the resource utilization is high.
The advantage of FPGA is in the storage bandwidth. Think of a common spartan-3A, 20k lut, each running to 200MHz, which is equivalent to 4000Gb/s bandwidth. The bandwidth of a first-level cache of an advanced CPU is worse than this. far. Now the most advanced FPGA, the performance is equivalent to 200 times this performance, think about how this is a BT beast. My idea is to do the same design and try to turn the logic into a distributed memory operation. In an optimized logic design, after converting logic into memory operations, resource utilization can be increased by a factor of 10. Of course, this transformation process must be realized. I have always stressed that to learn internal strength is to embody value in these transformation processes.
In addition, the storage thing, due to the relationship between company policy and position, can not be made now, this is not a technical problem, the technical solution has been there 3 years ago, but it has been destroyed, and then wait for the opportunity. By the way, the basic idea of ​​this storage is known to everyone, similar to LZW compression, but the sample is not 64k but very large, up to 2 to the 64th power, the retrieval process is very complicated, I just put the most complex The search process moved to the resolution of the other problem. The idea of ​​the retrieval process is to solve the problem of the search engine. To do storage is to use the retrieval process on LZW compression.
Recently verified this idea, resource utilization has increased by 8 times, I feel very scary, in spartan-3A, 2000 silices equivalent to 200,000 gates can achieve 16 Ethernet controller MAC with PLBDMA and PTP In the past, the optimal design can only be done 2, and the official xilinx can only do 0.5. The first thought progress, the resource utilization rate has increased by 4 times, the second progress has increased by 8 times. The thought is too powerful. I feel terrible.
The next step will be to use this idea to do some BT stuff.
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