Two misunderstandings of Verilog:
Use Reg type or Net type:
The Reg type is only assigned in the process block; the Net type is assigned or driven outside the process block.
Blocking assignments and non-blocking assignments:
The conditions under which competition occurs in Verilog: two or more statements result in different results when the execution order is different, and there is competition.
Nonblocking is not a type;
Blocking assignment is a one-step process that calculates RHS and makes LHS more uninterruptible.
Seven criteria:
1. Timing logic and latches, using non-blocking assignments
2. Combination logic in the always block, using blocking assignment
3. The same always block, the timing combination hybrid logic uses non-blocking assignments
4. In general, do not mix blocking and non-blocking assignments in the same always block.
5. Do not assign the same variable in multiple always blocks
6. Use $strobe to display non-blocking assignments worth signal
7. Do not use the #0 process assignment
Hierarchical event queues in Verilog:
Activity events: blocking assignments; calculating RHS for non-blocking assignments; continuous assignment; $display command; calculating input and changing the output of primitives. These events may be scheduled in any order.
Inactive events: Blocking assignments for #0 Non-blocking events: Updating LHS for non-blocking assignments
Monitoring events: $monitor command; $strobe command Experience:
Using non-blocking assignments in always blocks to generate timing logic and latches using blocking assignments in always blocks to generate combinational logic using non-blocking assignments in always blocks to produce timing and combinational logic in the same block in pure combinational logic Using non-blocking assignments can lead to functional errors
The way in which blocking and non-blocking assignments are mixed:
Combining combined logic assignments with timing expressions or separating combinatorial logic assignments from sequential logic, described in separate statement blocks. It is not recommended to mix blocking and non-blocking assignments in the same always block.
A few misconceptions about non-blocking assignments:
Error 1: Unable to use the $display command to display a positive solution for a non-blocking assignment variable: Update of a non-blocking assignment variable after all $display commands Error 2: #0 Let an assignment execute a positive solution at the end of each time step: #0 will only let Assignment statement enters inactive event queue Error 3: Multiple non-blocking assignments to the same variable in the same always block are not allowed positive solutions: the above assignment is defined in the IEEE 1364 verilog standard, and the last non-blocking assignment takes effect
Difficulties at the beginning of the simulation:
Different simulators, different simulation options lead to different phenomena when starting the simulation. Recommendation: Set the reset signal by non-blocking assignment at time 0;
The first half cycle sets the clock to 0.
Some experience in writing Verilog code:
Verilog file name and module name are the same. Do not use casex statements in synthesizable code. When using casez statements in synthesizable code, be careful when writing case statements. Use casez for cases that don't care, use ? instead of Z to indicate no Concerned cases
Verilog writes state machine related:
State machine classification: Moore (output is only related to current state) and Mealy (output is related to current state and input)
Basic block of binary code and One-Hot code state machine: next state degree combination logic; current state logic of clock synchronization; output combination logic two always block write state machines, using three always blocks, if the output needs to be registered and used efficiently One-Hot status encoding, combined output experience:
Each state machine is pre-defined as a separate Verilog module. The state assignment uses the state name as a parameter. Do not use `define, use parameter more.
The state machine of two always statement blocks, an always used to describe the timing logic of the state vector register. One is used to describe the next state degree combinational logic. The combined output can be described by a continuous assignment statement or in the next state combination combination always block.
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