FPGA structure characteristics and development I want to explain this topic, the internal of the FPGA has its corresponding fabric, how to use it in the development process to the maximum extent possible.
Some of them were learned by reading the XAPP manual provided on the XILINX website. I am talking about them again here because it is really easy to use.
SRL16 is very convenient in implementing delay and closed-loop implementation of duty cycle controllable trigger pulses. By instantiating it in the code, the code is relatively simple. It is also convenient to adjust the delay amount during debugging. The use of it to pay attention to is that its Tcko is relatively large, it will be a bottleneck for timing. In order to avoid weaknesses, add a trigger DFF in the appropriate place, and then use it.
2.STARTUPThe STARTUP module is unfamiliar to many people and is rarely used in actual design. But if you use it, it will bring great reliability and coding simplicity to the design. I understand that a friend "rejects" it because it can't be simulated, and it really causes a lot of trouble in the simulation. Actually, MODELSIM supports it for simulation. To get a good idea of ​​it, you can search for a document on how to use it on the Internet, "Verilog GSR/GTS SimulaTIon Methodology". Many people have used MCU and DSP chips. STARTUP is equivalent to the global reset management unit inside these devices. . But STARTUP has a more advantageous side than them, saving routing resources while saving time to generate bitstreams.
3.BRAMBRAM is a very bullish thing, it can achieve complex mathematical operations, you can refer to "interpolation lookup table: a simple way to achieve DSP functions"; some complex large logic can be implemented in BRAM; fitting operations can also be efficient achieve. To use it efficiently, you can instantiate it directly in your design, but this is not the best approach. The XST tool has a corresponding comprehensive constraint syntax, which can be described in the HDL language in the code. When it is integrated, it tells XST to integrate it into BRAM.
4. Global clock related primitivesInvolving the design content of the clock, we must adopt the instantiation method, which is also the current mainstream design method. In addition, FPGAs are growing rapidly, and XILINX has introduced a number of innovative devices that offer a wide variety of BUFs, such as BUFH, BUFIO, and more. Be sure to read the data carefully before using them, because their use is strictly required for IO or IO BANK. Some BUFs can only be connected to specific pins, otherwise the MAP phase in PROCESS cannot pass. This will not only develop the time, but also the PCB.
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