DAC and its buffers help improve system performance and simplify design

This article examines a new precision 16-bit DAC and talks about the output buffer of a high-speed complementary current-output DAC that is comparable to a transformer.

Voltage-switching 16-bit DAC provides low noise, fast settling time and better linearity

Based on the breakthrough 10-bit CMOSAD7520, which has been in use for nearly 40 years, the resistor ladder multiplying DAC was originally used for inverting op amps, while the amplifier's summing point (IOUTA) provides a convenient virtual ground (Figure 1).

Figure 1. CMOS Multiplying DAC Architecture

However, under certain constraints, they can also be used to provide a voltage switch configuration for the in-phase voltage output where the op amp acts as a voltage buffer (Figure 2). Here, the reference voltage VIN is applied to OUT, and the output voltage VOUT is supplied by VREF. A 12-bit version optimized for this use appeared shortly afterwards.

Figure 2. Multiplying DAC in voltage switching mode

Fast advance to the present: With the increasing popularity of single-supply systems, designers face the challenge of controlling power consumption while maintaining performance levels at high voltages. There is also an increasing demand for higher resolution (up to 16 bit) devices that can be used in this mode.

A significant advantage of using a multiplying DAC in voltage switching mode is that no signal inversion occurs, so a positive reference voltage will result in a positive output voltage. However, when used in this mode, the R-2R ladder architecture also has a drawback. In the case of the same DAC for current steering mode, the non-linear resistance of the N-channel switch in series with the R-2R ladder resistor will cause the integral linearity (INL) to drop.

In order to overcome the shortcomings of multiplying DACs while maintaining the advantages of voltage switching, a new high-resolution DAC, such as the AD5541A, has been developed (see Figure 3). The AD5541A uses a partially segmented R-2R ladder network and complementary switches to achieve ±1-LSB accuracy at 16-bit resolution and no adjustment over the entire temperature range of ?40°C to +125°C. The noise value is 11.8 nV/√Hz, and the setup time is 1?s.

Figure 3. AD5541A architecture

Performance characteristics

Settling time: Figure 4 and Figure 5 compare the settling time of the multiplying DAC in voltage mode and the settling time of the AD5541A. When the capacitive load on the output is minimum, the setup time of the AD5541A is approximately 1?s.

Figure 4. Settling time of the multiplying DAC

Figure 5. Setup time of the AD5541A

Noise Spectral Density: Table 1 compares the noise spectral density of the AD5541A and the multiplying DAC. The AD5541A has a slightly better performance at 10 kHz and is very advantageous at 1 kHz.

Table 1. Noise Spectral Density of AD5541A and Multiplying DAC

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