Optical Burst Switching (OpTIcal Burst Switching, OBS)
Optical burst switching (OpTIcal Burst Switching, OBS) is a new technology proposed in recent years. It uses a bandwidth granularity between optical circuit switching and optical packet switching. It transmits control packets on independent channels and carries them through control packets The reserved information is reserved for burst packets on the passing core nodes, and the burst packets pass through the entire OBS network in the form of pass-through in the optical domain. The core node only needs to perform E / O / E conversion and processing on the control packet, which overcomes the switching bottleneck in the optical circuit switching, improves the bandwidth utilization, and is easier to implement than the optical packet switching. The choice between the balance.
The assembly of burst packets is a key technology of OBS, which directly affects the performance of OBS. Its core is the selection and implementation of assembly algorithms. In [1], several algorithms are proposed, and their respective advantages and disadvantages are compared. Among them, algorithm C-minimum burst length and maximum convergence time (Min-Burst-Max-Assembly-Period, MBMAP)-also considers the package Two parameters, long and assembly time, can not only effectively use the network bandwidth, but also avoid large network delays. It is a superior algorithm.
1 Burst packet format Burst packet is the basic unit of data transmission in OBS network, it is composed of some IP packets with the same attributes (such as QoS level, destination node address, etc.) [2]. Each burst packet is equipped with a control packet (Burst Control Packet, BCP), which is sent before the burst packet, which carries some information of the burst packet (such as length, destination edge node address, etc.), used to pass The core node reserves resources for the burst packet, and then sends the burst packet after an offset time, the payload can be transmitted in the optical domain in a straight-through form, thereby reducing the core node E / O / E conversion and power. The burden of domain processing.
Regarding the format of the burst packet, there is currently no unified standard. The format discussed in this article is shown in Figure 1.
Figure 1 Burst packet format diagram BT is the burst packet type, NOP is the number of IP packets contained in the burst packet, Payload is the payload, and BL is the payload length. The burst packet type is classified according to the QoS level of the IP packet and the address of the destination edge node. There are M kinds of priorities and N edge nodes, then for any burst packet formed in any edge node, the destination edge node address has N−1 possibilities, so the burst packet assembled in each edge node There are M × (N−1) species.
2 Convergence and assembly of burst packages
The basic idea of ​​the MBMAP algorithm is that when the length of the accumulated IP packet exceeds the set minimum burst length MBL or the aggregation time exceeds, a control packet is sent out, and the burst packet is sent after the offset time offset TIme. The implementation method of the algorithm is discussed below.
2.1 Shared cache According to the previous assumption, each edge node has M × (N−1) types of burst packets. If a separate buffer is allocated for each type of burst packet, then as M and N increase Large, the required cache capacity will increase dramatically; on the other hand, due to the randomness of the IP packet type reaching the edge node, some caches may be idle at any time, while another part of the cache may lose data due to excessive burden . In this way, it not only reduces the performance of the network, but also wastes a lot of resources.
In order to improve network performance and increase the utilization of cache resources, a shared cache approach can be adopted [3]. The basic idea is to configure the number of caches for each edge node to K (where K is a positive integer less than M × (N−1)). When an IP packet arrives, the switching matrix depends on its type and the current cache The state of decides which cache to send it to, as shown in Figure 2. The line card is the interface between the OBS edge node and the external Ethernet. The configuration of the cache before the switching matrix is ​​to facilitate the switching matrix to identify the header information of the IP packet and to achieve the rate matching between the line card and the aggregation cache.
The use of dynamic caching requires that each aggregation cache be marked with a dynamic tag to indicate that the current state of each cache is empty or that some type of burst packet is being assembled in the cache. When an IP packet arrives, the switch matrix polls the current status of each aggregation buffer. If a burst queue to be assembled in a cache is found to be the same as the current IP packet type, the packet is sent to the queue; if not If a matching burst queue is found, the IP packet is sent to an idle buffer, a new burst packet assembly queue is started, and the buffer is marked accordingly. Because the buffer in front of the switching matrix and the subsequent burst aggregation cache are not in a one-to-one correspondence, the type of burst packets in the same aggregation cache at any time is also uncertain, so the polling algorithm of the switch matrix and the subsequent sending module is increased Complexity.
Figure 2 Schematic diagram of shared cache implementation
2.2 Convergence algorithm This paper makes appropriate adjustments to the MBMAP algorithm described in [1] for the specific implementation of the MBMAP algorithm. Let BLi be the length of the i-th burst queue being assembled in the current queue, PLi is the length of the IP packet currently arriving, TI is the current value of the timer, and T is the timing threshold. When an IP packet of type i arrives, the assembly algorithm is described as follows:
Event :: Packet arrive (i)
if (BLi = 0) then
Beginning the timer;
Set the flag of the queue;
end if;
BLi = BLi + PLi;
if (BLi> MBL or ti> T) then
Generate a sending request;
Modify the flag of the queue;
end if;
Assemble the packet to the queue;
Event :: received response (i)
Read out the burst;
Clear and stop the timer;
Clear the flag of the queue;
BLi = 0;
Event :: time out
if (no writing presently) then
Generate a sending request;
Modify the flag of the queue;
end if;
Figure 3 is a state transition diagram implemented by the algorithm. The meaning of each state is: idle represents that the cache is empty; writeIP represents that an IP packet is being written to the queue; timerun represents that the timer is running; wait represents that the sending module is waiting for a response; con_write represents the last write to the queue after the request is sent One IP packet; wr_rd represents the response from the sending module when the last IP packet has not been written, and the burst packet is read while writing the last IP packet; readBurst represents the burst packet.
Figure 3 The state transition diagram of the assembly algorithm There are three places in the figure with the "group write completed" annotation. "Group write completed" is the transition condition, and the state machine has no output or the output remains unchanged; the remaining comments, the content above the horizontal line is the transfer Conditions, the content below is the state machine output. The initial state at power-on is idle. The two points that need to be explained in the figure are:
1) The request sent to the post-transmission module is not the last control packet sent, but only contains the information required by the control packet. The sending module first stores the information when it detects the request. When it detects that the sending port is free, it assembles the BHP according to the information in the request and sends it out. Then it reads and sends the burst packet after an offset time. Because the offset time information needs to be carried in the BHP, it must be assembled and sent until the offset time value can be determined.
2) Since the NOP and BL in the header information can only be determined at the end, in order to facilitate the control of the data read and write pointers, corresponding to each aggregation cache, a set of registers is additionally set to store the last formed header. When receiving the read signal from the post-transmission module, a two-way selector is used to send the packet header first, followed by the payload in the aggregation buffer (Payload).
Implementation of Burst Packet Assembly Algorithm in OBS Edge Node
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